Name
Abstract | ||
|---|---|---|
Advances in VLSI technology require changes in circuit test application methods or apparatus. The use of on-chip testing, called Built-in Testing or Built-in Self-Testing (BIST), has become popular. BIST techniques compact the output response of the circuit under test (CUT). Here we discuss a time compaction method called Hamming count (H-count). H-count encompasses all syndrome detectable faults. Simulation results and theoretical analysis illustrate the overall fault-detection potential of Hamming count. The proposed method presents simple and effective compaction technique. |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1007/BF00135231 | J. Electronic Testing |
Keywords | Field | DocType |
Built-in self test,compaction,index vector,spectral coefficients,syndrome | Hamming code,Computer science,In-circuit test,Electronic engineering,Compaction,Very-large-scale integration,Circuit under test,Built-in self-test | Journal |
Volume | Issue | Citations |
2 | 4 | 0 |
PageRank | References | Authors |
0.34 | 13 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wen-Ben Jone | 1 | 419 | 46.30 |
| Anita Gleason | 2 | 0 | 0.68 |