Name
Abstract | ||
|---|---|---|
This paper describes an execution cache that uses process migration between hardware and software contexts by way of run-time reconfiguration (RTR) of Field Programmable Gate Arrays (FPGAs). The feasibility of such a system is demonstrated using existing FPGAs by accelerating a cycle- based simulation of a Register Transfer Level (RTL) design description. Through the use of a common instruction set, each simulation process may be run in a software Virtual Machine (VM) or in a hardware Real Machine (RM). The implementation provides data for an empirical model used to examine the behavior of unimplemented parts of the system. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/FPL.2007.4380722 | FPL |
Keywords | Field | DocType |
field programmable gate arrays,common instruction set,cycle-based simulation,execution cache,field programmable gate arrays,hardware real machine,hardware/software process migration,register transfer level design description,register transfer level simulation,run-time reconfiguration,software virtual machine | Virtual machine,Instruction set,Cache,Computer science,Process migration,Real-time computing,Software,Register-transfer level,Control reconfiguration,Computer architecture,Parallel computing,Field-programmable gate array,Embedded system | Conference |
ISSN | Citations | PageRank |
1946-1488 | 0 | 0.34 |
References | Authors | |
1 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Aric D. Blumer | 1 | 2 | 1.11 |
| Cameron D. Patterson | 2 | 59 | 11.71 |