Name
Title | ||
|---|---|---|
A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects |
Abstract | ||
|---|---|---|
Modern nanometer integrated circuits are patterned by sub-wavelength lithography with significant shape deviation from drawn layouts. Full-chip parasitics extraction faces new challenges since shape distortions such as line end rounding and corner rounding cannot be accurately characterized by existing layout parameter extraction (LPE) techniques which assume perfect polygons. A new LPE method and efficient shape approximation algorithms are proposed to account for the shape distortions. Preliminary results verified by field solver simulations indicate that accuracy of parasitics extraction can be significantly improved. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ASPDAC.2010.5419805 | ASP-DAC |
Keywords | Field | DocType |
layout parameter extraction,integrated circuit manufacture,shape distortion,new lpe method,shape distortions,field solver simulation,efficient shape approximation algorithm,lithography,full-chip parasitics extraction,shape deviation,sub-wavelength lithography effects,line end rounding,new challenge,sub-wavelength lithography effect,parasitics extraction,nanometer integrated circuits,significant shape deviation,new method,resistance,image recognition,shape,chip,layout,integrated circuit,soc | Polygon,Computer science,Shape approximation,Electronic engineering,Rounding,Lithography,Solver,Integrated circuit,Parasitic extraction,Wavelength | Conference |
ISSN | ISBN | Citations |
2153-6961 | 978-1-4244-5767-0 | 0 |
PageRank | References | Authors |
0.34 | 7 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kuen-Yu Tsai | 1 | 5 | 1.22 |
| Wei-Jhih Hsieh | 2 | 0 | 0.34 |
| Yuan-Ching Lu | 3 | 0 | 0.34 |
| Bo-Sen Chang | 4 | 47 | 2.99 |
| Sheng-Wei Chien | 5 | 1 | 0.68 |
| Yi-Chang Lu | 6 | 176 | 26.82 |