Paper Info
Title
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip.
Abstract
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a System-on-Chip that integrates variable size packet buffering, specialised cores for header and field processing, generic RISC cores and scheduling blocks. We focus on the main innovation, the reprogrammable pipeline module, and discuss its internal architecture, optimised to perform field processing on byte streams, as well as protocol processing on complex data structures. Furthermore, we present how modern and new tools were used in system dimensioning, design, and verification phases. The chip is able to handle up to 512K flows organised in individual queues. It embeds 5 custom cores optimised for field processing, 3 typical RISC cores for packet processing and 11 generic and application specific hardware blocks. It's been prototyped in UMC 0.18uCMOS technology in a 1096-pin BGA package and operates at 200MHz for 2.5Gbps links.
Year
DOI
Venue
2003
10.1109/DATE.2003.1186665
DATE
Field
DocType
Citations 
Byte,System on a chip,Scheduling (computing),Computer science,Network packet,Parallel computing,Real-time computing,Chip,Packet processing,Reduced instruction set computing,Header,Embedded system
Conference
2
PageRank 
References 
Authors
0.51
2
9
Name
Order
Citations
PageRank
G. Lykakis1102.62
N. Mouratidis220.51
kyriakos g vlachos36614.79
Nikos A. Nikolaou4776.40
Stylianos Perissakis5665.31
G. Sourdis620.51
George E. Konstantoulakis7324.31
Dionisios N. Pnevmatikatos8982106.40
Dionisios I. Reisis910411.09