Name
Abstract | ||
|---|---|---|
The Scalable Communications Core (SCC) is a power- and area-efficient solution for physical layer (PHY) and lower MAC processing of concurrent multiple wireless protocols. Our architecture consists of coarse-grained, heterogeneous, programmable accelerators ... |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ISVLSI.2007.9 | ISVLSI |
Keywords | Field | DocType |
enable systemc,lower mac processing,physical layer,concurrent multiple wireless protocol,area-efficient solution,scalable communications core,vhdl co-simulation,programmable accelerator,hardware description languages,electronics industry,hardware,software design,computational modeling,process design,system testing,system level design,design methodology,system design | Design language,ModelSim,Computer architecture,Software design,Software engineering,Computer science,Electronic system-level design and verification,SystemC,Platform-based design,VHDL,Hardware description language | Conference |
ISSN | ISBN | Citations |
2159-3469 | 0-7695-2896-1 | 3 |
PageRank | References | Authors |
0.48 | 8 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Richard Maciel | 1 | 3 | 0.48 |
| Bruno Albertini | 2 | 18 | 3.42 |
| Sandro Rigo | 3 | 185 | 24.91 |
| Guido Araujo | 4 | 40 | 5.23 |
| Rodolfo Azevedo | 5 | 271 | 30.84 |