Name
Abstract | ||
|---|---|---|
Large time-constrained applications are highly computer-intensive and are often implemented as a complex organization of pipelined data parallel tasks on a pool of embedded processors, DSP processors, and FPGAs. The large number of design alternatives available at each task level, the application as a whole, and the special needs of the reconfigurable devices (such as the FPGA) make the manual synthesis of such systems very tedious.The automatic synthesis algorithm in this paper combines exact (MILP-based) and heuristic techniques to solve this problem, which basically involves (1) propagation of timing constraints; (2) pipelining the loops to meet throughput requirements; (3) resource selection and scheduling, keeping the processing requirements and the timing constraints in view; (4) scheduling the resources across the tasks to ensure maximum utilization; and (5) hiding the reconfiguration delays of the FPGAs.While the use of MILP techniques helps in getting high-quality results, combining them with heuristics ensures acceptable synthesis times, striking a good balance between quality of results and synthesis time. Our experimental evaluation of the algorithm shows an average 40% in resource cost reduction (compared to manual synthesis) with synthesis times from minutes to as low as a few seconds in some cases. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1145/375977.375979 | ACM Trans. Design Autom. Electr. Syst. |
Keywords | Field | DocType |
large time-constrained application,synthesis time,delay/cost table,acceptable synthesis time,automatic synthesis algorithm,pipelining,time-constrained synthesis,dsp processor,time- constrained synthesis,reconfigurable computing,hierarchical control data-flow graph,resource selection,additional key words and phrases: delay/cost table,large time-constrained heterogeneous adaptive,list scheduling,large number,timing constraint,mixed integer linear programming,manual synthesis,resource cost reduction,embedded processor,data flow graph,adaptive system | Digital signal processing,Computer science,Scheduling (computing),Real-time computing,Heuristics,Control reconfiguration,Distributed computing,Pipeline (computing),Heuristic,Adaptive system,Parallel computing,Algorithm,Reconfigurable computing | Journal |
Volume | Issue | ISSN |
6 | 2 | 1084-4309 |
Citations | PageRank | References |
7 | 0.54 | 11 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| u nagaraj shenoy | 1 | 55 | 4.77 |
| alok choudhary | 2 | 50 | 2.99 |
| Prithviraj Banerjee | 3 | 2763 | 337.99 |