Title
The fate of stacking
Abstract
The impending doom of CMOS scaling has semiconductor mavericks scrambling for alternative solutions to continue increasing the device density per chip. One serious candidate is 3D integration in which the planar manufacturing technology extends skyward into the third dimension, much like skyscrapers. Similarities between chip architecture and building architecture are plentiful, and the author draws some parallels between the two.
Year
DOI
Venue
2009
10.1109/MDT.2009.127
IEEE Design & Test of Computers
Keywords
Field
DocType
device density,chip architecture,planar manufacturing technology,alternative solution,building architecture,impending doom,serious candidate,cmos scaling,mass production,cmos technology,architecture,3d ic,chip,stacking
Architecture,Parallels,Scrambling,Computer science,CMOS,Electronic engineering,Chip,Cmos scaling,Three-dimensional integrated circuit,Electrical engineering,Stacking
Journal
Volume
Issue
ISSN
26
5
0740-7475
Citations 
PageRank 
References 
0
0.34
0
Authors
1
Name
Order
Citations
PageRank
David S. Kung116620.93