Name
Abstract | ||
|---|---|---|
The quality of IC testing can be improved by applying appropriate design strategies. In this paper, we present a testability-oriented routing methodology, which can be used to modify the IC layout so as to reduce the probability of test escape. A testability-oriented iterative channel routing tool based on this methodology has been developed. Example applications of this tool illustrating the methodology are also presented in the paper. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/ICVD.1995.512110 | VLSI Design |
Keywords | Field | DocType |
appropriate design strategy,testability-oriented routing methodology,testability-oriented iterative channel,testability-oriented channel routing,test escape,example application,ic layout,ic testing,cost function,iterative methods,integrated circuit layout,design strategies,design for testability,routing,fault detection,network routing,manufacturing | Design for testing,Integrated circuit layout,Testability,Multipath routing,Bridging fault,Iterative method,Computer science,Communication channel,Electronic engineering,Real-time computing,Routing (electronic design automation),Reliability engineering | Conference |
ISBN | Citations | PageRank |
0-8186-6905-5 | 3 | 0.54 |
References | Authors | |
7 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jitendra Khare | 1 | 39 | 5.41 |
| Sujoy Mitra | 2 | 8 | 2.41 |
| Pranab K. Nag | 3 | 47 | 5.94 |
| U. Maly | 4 | 3 | 0.54 |
| Rob A. Rutenbar | 5 | 2283 | 280.48 |