Name
Abstract | ||
|---|---|---|
Field-programmable gate arrays (FPGAs) are an important implementation medium for digital logic. Unfortunately, they currently suffer from poor silicon area utilization due to routing constraints. In this paper we present Triptych, an FPGA architecture designed to achieve improved logic density with competitive performance. This is done by allowing a per-mapping tradeoff between logic and routing resources, and with a routing scheme designed to match the structure of typical circuits. We show that, using manual placement, this architecture yields a logic density improvement of up to a factor of 3.5 over commercial FPGAs, with comparable performance. We also describe Montage, the first FPGA architecture to fully support asynchronous and synchronous interface circuits. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/92.475968 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
field-programmable gate array,triptych fpga architecture,competitive performance,architecture yield,comparable performance,fpga architecture,routing scheme,improved logic density,digital logic,commercial fpgas,logic density improvement,integrated circuit,integrated circuit design,process design,logic circuits,network routing,field programmable gate array,field programmable gate arrays,vlsi,logic design,silicon,routing,application specific integrated circuits | Logic synthesis,Logic gate,Computer architecture,Computer science,Field-programmable gate array,Application-specific integrated circuit,Electronic engineering,Integrated circuit design,Boolean algebra,Very-large-scale integration,Reconfigurable computing | Journal |
Volume | Issue | ISSN |
3 | 4 | 1063-8210 |
Citations | PageRank | References |
31 | 10.76 | 2 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gaetano Borriello | 1 | 6050 | 777.11 |
| Carl Ebeling | 2 | 1405 | 185.32 |
| Scott Hauck | 3 | 2539 | 232.71 |
| Steven M. Burns | 4 | 563 | 104.03 |