Name
Abstract | ||
|---|---|---|
As CMOS technology is pushed to its basic physical limits, alternate technologies are required for the realization of interconnect in future high performance integrated circuits. In this paper, we develop a generalized design technique for carbon nanotube (CNT) bundle-based interconnect, which we use to examine the performance limits and fabrication requirements for future nanotube-based interconnect solutions. The results indicate that optimized nanotube bundles can provide up to a 69% delay reduction in 22 nm process technology, and the optimal design method decreases delay by 21% and 29% on average compared to non-optimized multi-walled and single-walled CNT bundles. We also find that future CNT bundle fabrication processes must achieve a nanotube area coverage of at least 30% for optimized CNT bundles and 40% for non-optimized CNT bundles to obtain competitive performance results compared to copper interconnect. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ISCAS.2008.4541537 | ISCAS |
Keywords | Field | DocType |
CMOS integrated circuits,carbon nanotubes,integrated circuit interconnections,CMOS technology,CNT bundle fabrication processes,carbon nanotube bundle-based interconnect,integrated circuits,nonoptimized multi-walled CNT bundles,optimized carbon nanotube interconnect,single-walled CNT bundles | Nanotube,Computer science,Electronic engineering,CMOS,Copper interconnect,Carbon nanotube,Interconnection,Integrated circuit,Bundle,Fabrication | Conference |
ISSN | Citations | PageRank |
0271-4302 | 0 | 0.34 |
References | Authors | |
2 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yehia Massoud | 1 | 772 | 113.05 |
| Arthur Nieuwoudt | 2 | 207 | 20.59 |