Name
Abstract | ||
|---|---|---|
A 12b 2 MS/s cyclic ADC achieves low power consumption with a single-ended rail-to-rail input signal range of 3.3 Vp-p. The proposed voltage reference scheme directly employing power supply voltages implements an offset voltage less than 1 mV without well-known calibration and trimming techniques. The prototype ADC in a 0.18 mum CMOS technology demonstrates the effective number of bits of 11.48 for a 100 kHz full-scale input at 2 MS/s. The ADC with an active die area of 0.12 mm2 consumes 3.6 mW at 2 MS/s and 3.3 V(analog)/1.8 V (digital). |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/APCCAS.2008.4745949 | APCCAS |
Keywords | Field | DocType |
cmos integrated circuits,calibration,low power consumption,power 3.6 mw,analogue-digital conversion,frequency 100 khz,voltage 3.3 v,low-power electronics,cmos cyclic adc,voltage 1.8 v,low offset rail-to-rail,size 0.18 mum,trimming technique,calibration technique,voltage reference,single-ended rail-to-rail input signal range,word length 12 bit,capacitors,effective number of bits,low power electronics,generators,gain,prototypes | Capacitor,Input offset voltage,Computer science,Voltage,Voltage reference,CMOS,Effective number of bits,Electronic engineering,Trimming,Electrical engineering,Low-power electronics | Conference |
ISBN | Citations | PageRank |
978-1-4244-2342-2 | 1 | 0.37 |
References | Authors | |
4 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Young-Ju Kim | 1 | 268 | 29.56 |
| Hee-Cheol Choi | 2 | 26 | 10.68 |
| Pil-Seon Yoo | 3 | 1 | 1.04 |
| Dong-Suk Lee | 4 | 1 | 0.37 |
| Joong-Ho Choi | 5 | 42 | 10.78 |
| Seunghoon Lee | 6 | 244 | 61.57 |