Paper Info
Title
Revisiting Cache Block Superloading
Abstract
Technological advances and increasingly complex and dynamic application behavior argue for revisiting mechanisms that adapt logical cache block size to application characteristics. This approach to bridging the processor/memory performance gap has been studied before, but mostly via trace-driven simulation, looking only at L1 caches. Given changes in hardware/software technology, we revisit the general approach: we propose a transparent, phase-adaptive, low-complexity mechanism for L2 superloading and evaluate it on a full-system simulator for 23 SPEC CPU2000 codes. Targeting L2 benefits instruction and data fetches. We investigate cache blocks of 32-512B, confirming that no fixed size performs well for all applications: differences range from 5-49% between best and worst fixed block sizes. Our scheme obtains performance similar to the per application best static block size. In a few cases, we minimally decrease performance compared to the best static size, but best size varies per application, and rarely matches real hardware. We generally improve performance over best static choices by up to 10%. Phase adaptability particularly benefits multiprogrammed workloads with conflicting locality characteristics, yielding performance gains of 5-20%. Our approach also outperforms next-line and delta prefetching.
Year
DOI
Venue
2009
10.1007/978-3-540-92990-1_25
HiPEAC
Keywords
Field
DocType
best size,revisiting cache block superloading,worst fixed block size,scheme obtains performance,memory performance gap,logical cache block size,static size,performance gain,static block size,fixed size,best static choice
Block size,Adaptability,Locality,Cache,Computer science,Bridging (networking),Parallel computing,Real-time computing,Spec#,Performance gap,Context switch
Conference
Volume
ISSN
Citations 
5409
0302-9743
1
PageRank 
References 
Authors
0.37
19
3
Name
Order
Citations
PageRank
Matthew A. Watkins119914.88
Sally A. Mckee21928152.59
Lambert Schaelicke327920.23