Name
Abstract | ||
|---|---|---|
Scaling enhances intrinsic transistor performance and degrades interconnects. As the technology steps into nanometer era, global interconnects are becoming bottleneck for overall chip performance. In this paper, we show package level interconnects are an effective alternative for on-chip global wiring. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare performance - bandwidth, bandwidth density, latency and power consumption - of the package level transmission lines with conventional on-chip global interconnects for different ITRS technology nodes. Based on these results, we show package level interconnects are well suited for power demanding low latency applications and we analyze different interconnect options like memory buses, long inter tile interconnects, clock and power distribution. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1145/1053355.1053361 | SLIP |
Keywords | Field | DocType |
inter tile interconnects,degrades interconnects,overall chip performance,intrinsic transistor performance,on-chip global wiring,package level interconnects,light transmission,lc transmission line,conventional on-chip global interconnects,global interconnects,speed of light,package,transmission lines,transmission line,chip,low latency | Bottleneck,Computer science,Latency (engineering),Electronic engineering,Chip,Electric power transmission,Bandwidth (signal processing),Latency (engineering),Transistor,Interconnection | Conference |
ISBN | Citations | PageRank |
1-59593-033-7 | 3 | 0.50 |
References | Authors | |
6 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| J. Balachandran | 1 | 11 | 2.87 |
| S. Brebels | 2 | 13 | 4.25 |
| G. Carchon | 3 | 6 | 1.40 |
| T. Webers | 4 | 3 | 0.50 |
| W. De Raedt | 5 | 6 | 2.08 |
| B. Nauwelaers | 6 | 10 | 4.72 |
| E. Beyne | 7 | 29 | 5.72 |