Name
Abstract | ||
|---|---|---|
We built a high-speed, digital mean-field Boltzmann chip and SBus board for general problems in constraint satjsfaction and learning. Each chip has 32 neural processors and 4 weight update processors, supporting an arbitrary topology of up to 160 functional neurons. On-chip learning is at a theoretical maximum rate of 3.5 x 108 con(cid:173) nection updates/sec; recall is 12000 patterns/sec for typical condi(cid:173) tions. The chip's high speed is due to parallel computation of inner products, limited (but adequate) precision for weights and activa(cid:173) tions (5 bits), fast clock (125 MHz), and several design insights. |
Year | Venue | Keywords |
|---|---|---|
1993 | NIPS | constraint satisfaction |
Field | DocType | Citations |
SBus,Constraint satisfaction,Computer science,Chip,Artificial intelligence,Boltzmann constant,Very-large-scale integration,Machine learning | Conference | 0 |
PageRank | References | Authors |
0.34 | 2 | 10 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michael Murray | 1 | 0 | 0.34 |
| Ming-tak Leung | 2 | 0 | 0.34 |
| Kan Boonyanit | 3 | 0 | 0.34 |
| Kong Kritayakirana | 4 | 0 | 0.34 |
| James B. Burg | 5 | 0 | 0.34 |
| Gregory J. Wolff | 6 | 212 | 40.46 |
| Tokahiro Watanabe | 7 | 0 | 0.34 |
| Edward L. Schwartz | 8 | 32 | 7.47 |
| David G. Stork | 9 | 627 | 106.17 |
| Allern M. Peterson | 10 | 0 | 0.34 |