Name
Title | ||
|---|---|---|
A 10-b 100-MS/s pipelined ADC with an optimized bit-stage resolution in 65nm CMOS technology |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ISCAS.2010.5537644 | ISCAS |
Keywords | Field | DocType |
effective number of bits,cmos integrated circuits,linearity,signal to noise ratio,topology,capacitance,pipelines,operational amplifiers,spurious free dynamic range | Computer science,Sampling (signal processing),Linearity,Signal-to-noise ratio,CMOS,Spurious-free dynamic range,Electronic engineering,Effective number of bits,Successive approximation ADC,Computer hardware,Operational amplifier | Conference |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pasquale Delizia | 1 | 0 | 0.68 |
| Gianni Saccomanno | 2 | 0 | 0.34 |
| Stefano D'Amico | 3 | 129 | 27.42 |
| Andrea Baschirotto | 4 | 168 | 48.21 |