Name
Abstract | ||
|---|---|---|
In this paper we investigate and present the architecture design of a VLSI processor for Prolog based on the RISC concept. First the results of the analysis of several Prolog application programs are reported. Based on these results a reduced instruction set as well as the register and cache organisation of the Prolog RISC processor are presented. The evaluation of the performance of the Prolog RISC architecture shows that a performance comparable to those of complex sequential Prolog machines can be achieved. |
Year | DOI | Venue |
|---|---|---|
1989 | 10.1016/0165-6074(89)90028-8 | Microprocessing and Microprogramming |
Keywords | DocType | Volume |
Prolog,RISC processor,computer architecture,hardware for AI | Journal | 27 |
Issue | ISSN | Citations |
1 | 0165-6074 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Peter Deussen | 1 | 56 | 26.79 |
| Wolfgang Rosenstiel | 2 | 1462 | 212.32 |
| Klaus Erik Schaufer | 3 | 0 | 0.34 |
| Jörg Wedeck | 4 | 0 | 0.34 |