Paper Info
Title
Runtime verification for software transactional memories
Abstract
Software transactional memories (STMs) promise simple and efficient concurrent programming. Several correctness properties have been proposed for STMs. Based on a bounded conflict graph algorithm for verifying correctness of STMs, we develop TRACER, a tool for runtime verification of STM implementations. The novelty of TRACER lies in the way it combines coarse and precise runtime analyses to guarantee sound and complete verification in an efficient manner. We implement TRACER in the TL2 STM implementation. We evaluate the performance of TRACER on STAMP benchmarks. While a precise runtime verification technique based on conflict graphs results in an average slowdown of 60x the two-level approach of TRACER performs complete verification with an average slowdown of around 25x across different benchmarks.
Year
DOI
Venue
2010
10.1007/978-3-642-16612-9_32
RV
Keywords
Field
DocType
conflict graphs result,average slowdown,stm implementation,precise runtime analysis,runtime verification,precise runtime verification technique,complete verification,software transactional memory,tl2 stm implementation,stamp benchmarks,bounded conflict graph algorithm
Computer science,Parallel computing,Correctness,Implementation,Real-time computing,Transactional memory,Runtime verification,Software,Concurrent computing,Transactional leadership,Bounded function
Conference
Volume
ISSN
ISBN
6418
0302-9743
3-642-16611-3
Citations 
PageRank 
References 
0
0.34
21
Authors
1
Name
Order
Citations
PageRank
Vasu Singh11869.36