Name
Abstract | ||
|---|---|---|
Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML quaternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaviour. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ISMVL.2007.30 | ISMVL |
Keywords | Field | DocType |
proper design,correct behaviour,attractive application,advanced circuit,correct evaluation,rtd-based quaternary inverters,usual mml circuit topology,circuit representative parameter,monostable-to-multistable transition logic,mml quaternary inverter,multiple-valued logic,voltage,circuit topology,logic circuits,temperature | Digital electronics,Diode–transistor logic,Logic gate,Pass transistor logic,Logic optimization,Computer science,Electronic engineering,Resistor–transistor logic,Logic family,Asynchronous circuit | Conference |
ISBN | Citations | PageRank |
0-7695-2831-7 | 1 | 0.36 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Juan Nunez | 1 | 12 | 3.98 |
| Jose M. Quintana | 2 | 28 | 3.14 |
| Maria J. Avedillo | 3 | 38 | 10.61 |