Name
Abstract | ||
|---|---|---|
A platform named USAT that integrates several gate-level and RTL satisfiability solvers is described. USAT has a unified circuit model that can represent both gate-level and RTL circuits. USAT integrates other solvers by translating between various circuit formats via the unified circuit model. USAT also includes a circuit generator that can generate RTL circuits with specific features specified by users. USAT also has a native ATPG-based solver that can solve satisfiability problem at both gate-level and RTL. The effectiveness of USAT is demonstrated by applications in bounded model checking. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/CSSE.2008.1352 | CSSE (4) |
Keywords | Field | DocType |
atpg-based solver,gate-level satisfiability solver,specific feature,various circuit format,model checking,satisfiability solving,rtl satisfiability solver,rtl circuit,automatic test pattern generation,native atpg-based solver,gate-level circuits,rtl satisfiability usat,rtl circuits,computability,satisfiability,circuit cad,circuit generator,rtl (register transfer level),bounded model checking,circuit formats,unified circuit model,integrated platform,satisfiability problem,formal verification,logic gates,computational modeling,generators,register transfer level,data structures,design automation | Automatic test pattern generation,Data structure,Model checking,Programming language,Computer science,Boolean satisfiability problem,Computability,Electronic design automation,Solver,Formal verification | Conference |
Volume | ISBN | Citations |
4 | 978-0-7695-3336-0 | 0 |
PageRank | References | Authors |
0.34 | 9 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wei-Min Wu | 1 | 0 | 0.34 |
| Min-Chuan Chen | 2 | 0 | 0.34 |