Name
Abstract | ||
|---|---|---|
System on a Chip (SoC) has become a reality, facing design of complex circuits into a single programmable device, supporting different cores for microprocessors, interface, bus, etc. However, the automatic inclusion of new general cores from different providers via a standard bus still needs a reliable interface mechanism to guarantee the correct protocol conversion and performance. This work presents a CAD tool to cope this problem based on a Petri Net protocol conversion approach in a high level behavioral specification, focusing on bus planning and core integration. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/SBCCI.2003.1232818 | SBCCI |
Keywords | Field | DocType |
Petri nets,hardware description languages,industrial property,integrated circuit design,logic CAD,protocols,system buses,system-on-chip,CoreBond CAD tool,IP-core integration methodology,IP-core reuse,Petri net protocol conversion,SoC design,VHDL,bus planning,core integration,high level behavioral specification,interfaces,microprocessors,system on a chip | Cad tools,Computer architecture,Petri net,System on a chip,Computer science,Real-time computing,Electronic engineering,Integrated circuit design,Industrial property,Electronic circuit,Embedded system,Hardware description language | Conference |
ISBN | Citations | PageRank |
0-7695-2009-X | 0 | 0.34 |
References | Authors | |
5 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Julio A. De Oliveira Filho | 1 | 12 | 2.97 |
| Manoel Eusebio de Lima | 2 | 29 | 8.12 |
| Paulo Romero Martins Maciel | 3 | 363 | 59.24 |
| Juliana Moura | 4 | 0 | 0.34 |
| Bruno Celso | 5 | 0 | 0.34 |