Name
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ITA.2011.5743586 | ITA |
Keywords | Field | DocType |
DRAM chips,Reed-Solomon codes,circuit complexity,decoding,error correction codes,error statistics,fault diagnosis,mainframes,memory architecture,parity check codes,DRAM,Reed-Solomon code,array code,catastrophic memory module failure,computer memory storage,decoding complexity,diff-MDS code,dynamic random access memory,error control code,mainframe,memory chip failure,memory resiliency,parity code,single bit error | Mathematical optimization,Interleaved memory,Computer science,Parallel computing,Memory management,Memory map,Memory address,Flat memory model,Computer engineering,Computer memory,Redundant array of independent memory,Memory architecture | Conference |
Citations | PageRank | References |
4 | 0.54 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Luis Alfonso Lastras-Montaño | 1 | 276 | 14.48 |
| Patrick J. Meaney | 2 | 30 | 3.71 |
| Eldee Stephens | 3 | 4 | 0.54 |
| Barry M. Trager | 4 | 614 | 97.81 |
| James A. O'Connor | 5 | 4 | 0.54 |
| Luiz C. Alves | 6 | 94 | 11.32 |