Name
Abstract | ||
|---|---|---|
This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compatible faults based on necessary assignments. It guides the justification and propagation decisions to create patterns that will accommodate most targeted faults. The technique presented achieves close to minimal test pattern sets for ISCAS circuits. For industrial circuits it achieves much smaller test pattern sets than other methods in designs sensitive to decision order used in ATPG. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/DATE.2009.5090834 | DATE |
Keywords | Field | DocType |
automatic test pattern generation,fault diagnosis,integrated circuit testing,logic design,ATPG,ISCAS circuits,automatic test pattern generator,decision order,industrial circuits,propagation decision,scalable method,scan based circuits,small test set generation,stuck-at faults,test pattern sets | Logic synthesis,Automatic test pattern generation,Logic gate,High-level design,Computer science,Field-programmable gate array,Triple modular redundancy,Real-time computing,Single event upset,Scalability | Conference |
ISSN | Citations | PageRank |
1530-1591 | 1 | 0.36 |
References | Authors | |
8 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Santiago Remersaro | 1 | 208 | 7.95 |
| Janusz Rajski | 2 | 2460 | 201.28 |
| Sudhakar M. Reddy | 3 | 5747 | 699.51 |
| Irith Pomeranz | 4 | 3829 | 336.84 |