Paper Info
Title
Non-volatile memory reduction based on 1-D memory space mapping of a specific set of QC-LDPC codes.
Abstract
Supporting a great diversity of multi-rate H-matrices for multiple communication protocols requires a large amount of non-volatile memory, which may consume a large silicon area or logic elements and constrain the implementation of an overall decoder. Therefore, schemes for memory reduction are necessary to make the parity-check storage more compact. This study proposes a specific set of quasi-cyclic low-density parity-check (LDPC) (QC-LDPC) codes which can transfer a traditional two-dimensional (2-D) parity-check matrix (H-matrix) into a one-dimensional (1-D) memory space. Compared to the existing schemes, the proposed codes and memory reduction scheme do achieve significant reduction rates. Within a fixed memory space, many more H-matrices for diverse communication protocols can be saved via the proposed QC-LDPC codes, which are well constructed from modified Welch-Costas sequences. Furthermore, relatively good error performances, which outperform computer-generated random LDPC codes and Sridhara-Fuja-Tanner codes, are also shown in our simulation results. Consequently, we conclude that the proposed QC-LDPC codes can enlarge the capacity for saving much more low-BER (bit error rate) H-matrices within a fixed memory space.
Year
DOI
Venue
2012
10.1186/1687-1499-2012-191
EURASIP J. Wireless Comm. and Networking
Keywords
Field
DocType
Actual Address, Memory Space, LDPC Code, Gate Count, Similar Code
Concatenated error correction code,Gate count,Computer science,Low-density parity-check code,Parallel computing,Block code,Turbo code,Theoretical computer science,Real-time computing,Non-volatile memory,Linear code,Bit error rate
Journal
Volume
Issue
ISSN
2012
1
1687-1499
Citations 
PageRank 
References 
12
0.35
10
Authors
4
Name
Order
Citations
PageRank
Chung-Ping Young110517.78
Chung-Chu Chia2120.69
Chao-Chin Yang36414.24
Chun-Ming Huang4120.35