Name
Abstract | ||
|---|---|---|
Resetting flip flops in high speed clock domain across wide silicon area is a challenge due to significant delay variations between the clock and reset signals. In this paper, a novel method of transmitting Reset Through the Clock (RTC) tree is proposed. At the root of the clock tree, multiplexing circuit encodes reset as pulses of width smaller than clock pulses whereas in the non-reset mode it passes the clock pulses unaltered. RTC avoids a separate reset tree. Extractor circuits at the leaf levels of the clock tree selectively decode the reset mode pulses which are applied to flip flop reset pins. This scheme has additional tolerance to the above mentioned delay variations, has low latency, saves reset pins between blocks on System on Chips (SoCs) and needs lesser global routing resources. The proposed method has been demonstrated on a testchip fabricated in TSMC 40nm process. System level measurements in the lab at clock rate of 1GHz prove that this technique works as robustly as traditional reset method. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/VLSID.2013.166 | VLSI Design |
Keywords | Field | DocType |
clocks,flip-flops,system-on-chip,clock pulse,clock tree,flip flop reset pins,flip flop resetting,high speed clock domain,latency,multiplexing circuit encodes reset,nonreset mode,reset signal,silicon area,system on chips,SoC,clock,latency,on-chip delay variation,reset | Clock gating,Power-on reset,Computer science,Clock domain crossing,Electronic engineering,Real-time computing,Synchronous circuit,Clock skew,Digital clock manager,CPU multiplier,Clock rate | Conference |
ISSN | Citations | PageRank |
1063-9667 | 1 | 0.39 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sanku Mukherjee | 1 | 19 | 3.98 |
| M. Thrivikraman M. | 2 | 1 | 0.39 |
| Anil K. Goyal | 3 | 1 | 0.39 |
| Arul Sendhil | 4 | 19 | 4.31 |