Paper Info
Title
A 5-bit 1.5GSps calibration-less binary search ADC using threshold reconfigurable comparators.
Abstract
Modern RF communication technologies often shift the baseband processing to the digital domain, thus requiring an analog-to-digital converter (ADC) as interfacing element. For most applications, those ADCs must provide very-high conversion rate at low cost (effective in terms of area and power). We propose an improved binary-search ADC topology, which relies on a pipeline of threshold-reconfigurable comparators and a time-interleaved track-and-hold arrangement. We also propose a topology of threshold-reconfigurable comparator and a corresponding effective design methodology based on optimization through genetic algorithms. In this paper, we design a proofof- concept 5-bit ADC which does not require calibration as most similar designs. Monte Carlo simulations for the proposed design show that, sampling at 1.5 GSps, the ADC consumes 5 mW providing 4.6 effective bits and a figure of merit of 138 fJ/conversion step (mean values).
Year
DOI
Venue
2013
10.1109/ISCAS.2013.6571856
ISCAS
Keywords
Field
DocType
Monte Carlo methods,analogue-digital conversion,comparators (circuits),genetic algorithms,network synthesis,sample and hold circuits,Monte Carlo simulation,RF communication technology,analog-to-digital converter,baseband processing,binary-search ADC topology,calibration-less binary search,genetic algorithm,interfacing element,optimization,power 5 mW,threshold-reconfigurable comparator pipeline,time-interleaved track-and-hold arrangement,word length 4.6 bit,word length 5 bit
Flight dynamics (spacecraft),Baseband,Comparator,Computer science,Network synthesis filters,Interfacing,Electronic engineering,Figure of merit,Binary search algorithm,Successive approximation ADC
Conference
ISSN
Citations 
PageRank 
0271-4302
1
0.44
References 
Authors
0
4
Name
Order
Citations
PageRank
Taimur Gibran Rabuske1286.53
Fabio Gibran Rabuske210.44
Jorge R. Fernandes315434.16
Cesar Ramos Rodrigues4307.05