Title
An ultralow-power 10-Gbits/s LVDS output driver
Abstract
This paper describes a new topology and implementation of a 10-Gbits/s low-voltage differential-signaling (LVDS) voltage-mode output driver designed for high-speed data-transfer applications. Using a positive-feedback technique, the driver achieves ultralow-power operation while maintaining the proper internal chip impedance required for matching the line impedance. As a result, signal reflection is minimized, and good signal integrity is achieved. The driver, which consists of a predriver and an output stage, consumes a total of 15.63-mW at-speed power. In measurements, the driver, which was a part of an equalizer chip, achieved a peak-to-peak jitter of 11 ps at 10 Gbits/s and a return-loss performance of less than --15 dB. It provides a single-ended output swing of 400 mV and a common-mode voltage of 1.25 V, which are compliant with LVDS standards. The chip is fabricated in a standard 2.5-V/1.2-V SiGe BiCMOS technology with 100-GHz peak ft and is packaged in a commercial LLP package.
Year
DOI
Venue
2010
10.1109/TCSI.2009.2015721
IEEE Trans. on Circuits and Systems
Keywords
Field
DocType
lvds output driver,signal reflection,proper internal chip impedance,lvds standard,good signal integrity,single-ended output swing,line impedance,100-ghz peak ft,output stage,voltage-mode output driver,equalizer chip,ultralow-power 10-gbits,voltage,topology,low power electronics,chip,jitter,signal integrity,common mode,feedback,packaging,data transfer,common mode voltage,impedance matching,positive feedback,impedance,reflection
Signal reflection,Signal integrity,Impedance matching,Electronic engineering,Chip,Common-mode signal,Low-voltage differential signaling,Jitter,Electrical engineering,Mathematics,Low-power electronics
Journal
Volume
Issue
ISSN
57
1
1549-8328
Citations 
PageRank 
References 
1
0.44
3
Authors
5
Name
Order
Citations
PageRank
Khaldoon Abugharbieh1146.37
Shoba Krishnan27911.81
Jitendra Mohan3479.34
Varadarajan Devnath410.44
Ivan Duzevik510.77