Name
Abstract | ||
|---|---|---|
next generation wireless systems will lead to an integration of existing networks, forming a heterogeneous network. Re-configurable systems will be the enabling technology sharing hardware resources for different purposes. This paper will highlight the requirements of a re- configurable multi-standard terminal from the physical-layer point of view. A re -configurable architecture consisting of algorithm domain specific accelerators, allowing autonomous complex digital signal processing without interference from a microprocessor , will be explained. Performance comparison numbers with latest Digital Signal Processors will show the effectiveness of the proposed architecture. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/PIMRC.2002.1046671 | PIMRC |
Keywords | Field | DocType |
digital signal processing chips,reconfigurable architectures,software architecture,software radio,telecommunication standards,DSP,algorithm domain specific accelerators,digital signal processing,digital signal processors,heterogeneous network,microprocessor,physical-layer,reconfigurable architecture,reconfigurable multi-standard radios,reconfigurable systems,software radio,wireless systems | Architecture,Digital signal processing,Digital signal processor,Computer science,Software-defined radio,Microprocessor,Real-time computing,Interference (wave propagation),Software architecture,Heterogeneous network,Embedded system | Conference |
Volume | Citations | PageRank |
1 | 5 | 0.82 |
References | Authors | |
2 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jörg Brakensiek | 1 | 89 | 8.94 |
| Bernhard Oelkrug | 2 | 5 | 0.82 |
| Martin Bücker | 3 | 15 | 2.40 |
| Dirk Uffmann | 4 | 5 | 0.82 |
| A. Dröge | 5 | 5 | 0.82 |
| M. Darianian | 6 | 6 | 1.36 |
| Marius Otte | 7 | 5 | 0.82 |