Name
Abstract | ||
|---|---|---|
In systems typified by software defined radio, existing flows for run-time FPGA reconfiguration limit resource efficiency whenconstructinga varietyofdatapaths. Ourapproachallo- cates a sandbox region in which modules from a library can be flexibly placed and interconnected. An efficient run-time framework makes use of lightweight placement and routing techniques to respond on-demand to application requests. Compile time tools automate the task of adding interface wrappers to modules, insulating the designer from reconfig- uration details. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/FPL.2007.4380705 | FPL |
Keywords | Field | DocType |
field programmable gate arrays,logic CAD,program compilers,software radio,lightweight placement,program compiler,reconfigurable computing,run-time FPGA reconfiguration,run-time communication synthesis,software defined radio | Software-defined radio,Computer science,Real-time computing,Control reconfiguration,Sandbox (computer security),Computer architecture,On demand,Compile time,Resource efficiency,Parallel computing,Field-programmable gate array,Reconfigurable computing,Embedded system | Conference |
ISSN | Citations | PageRank |
1946-1488 | 13 | 1.02 |
References | Authors | |
5 | 9 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Peter M. Athanas | 1 | 231 | 34.97 |
| J. Bowen | 2 | 16 | 1.44 |
| T. Dunham | 3 | 16 | 1.44 |
| Cameron D. Patterson | 4 | 59 | 11.71 |
| J. Rice | 5 | 16 | 1.44 |
| M. Shelburne | 6 | 16 | 1.44 |
| J. Surís | 7 | 16 | 1.44 |
| Mark B. Bucciero | 8 | 15 | 1.40 |
| Jonathan Graf | 9 | 14 | 1.74 |