Paper Info
Title
A 10-Bit 205-Ms/S 1.0-Mm(2) 90-Nm Cmos Pipeline Adc For Flat Panel Display Applications
Abstract
This paper describes a 10-bit 205-MS/s pipeline analog-to-digital converter (ADC) for flat panel display applications with the techniques to alleviate the design limitations in the deep-submicron CMOS process. The switched source follower combined with a resistor-switch ladder eliminates the sampling switches and achieves high linearity for a large single-ended input signal. Multistage amplifiers adopting the complementary common-source topology increase the output swing range with lower transconductance variation and reduce the power consumption. The supply voltage for the analog blocks is provided by the low drop-out regulator for a high power-supply rejection ratio (PSRR) under the noisy operation environment. The pipeline stages of the ADC are optimized in the aspect of power consumption through the iterated calculation of the sampling capacitance and transconductance. The ADC occupies an active area of 1.0 mm(2) in a 90-nm CMOS process and achieves a 53-dB PSRR for a 100-MHz noise tone with the regulator and a 55.2-dB signal-to-noise-and-distortion ratio for a 30-MHz 1.0-V-PP single-ended input at 205 MS/s. The ADC core dissipates 40 mW from a 1.0-V nonregulated supply voltage.
Year
DOI
Venue
2007
10.1109/JSSC.2007.908760
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Keywords
DocType
Volume
amplifiers, analog-to-digital converter (ADC), buffer circuits, CMOS analog integrated circuits, integrated circuit testing, low drop-out regulator, low power, low voltage, noise measurement, pipeline stage optimization, power-supply rejection ratio (PSRR), sample-and-hold (S/H) circuits, switched-capacitor circuits
Journal
42
Issue
ISSN
Citations 
12
0018-9200
26
PageRank 
References 
Authors
2.14
8
4
Name
Order
Citations
PageRank
Seung-Chul Lee112418.27
Young-Deuk Jeon29813.50
Jong-Kee Kwon315823.10
Jongdae Kim410217.00