Paper Info
Title
A Study of Leveraging Memory Level Parallelism for DRAM System on Multi-core/Many-Core Architecture
Abstract
DRAM system has been more and more critical on modern multi-core/many-core architecture where the Moore's law has been made effect on increasing the number of cores integrated in a processor chip. The performance of DRAM system is usually measured in term of bandwidth and latency, which are regarded as inherently depending on Row Buffer Hit Rate (RBHR) according to previous studies. In this paper, we find that Memory Level Parallelism (MLP) exhibits a stronger correlation with the performance of DRAM system on multi-core/many-core architecture than RBHR, and promoting MLP significantly improves DRAM system performance. In order to exploit the MLP, we have evaluated various approaches including multi-bank, multi-row-buffers, multi-memory-controllers and the obsolete Virtual Channel Memory (VCM). The experimental results show that VCM is a better alternative to traditional DRAM chip on multi-core/many-core architecture than the other three approaches because VCM has almost all the advantages of the others: 1) it can improve homogeneous workloads' IPC by 2.21X on a 16-core system with 32 virtual channels due to leveraging unexploited MLP. 2) It can also promote Quality-of-Service (QoS) of DRAM system by removing unfairness while memory controllers serve memory requests. 3) It can save energy and has low area costs. Unfortunately, VCM, which was proposed in the late 1990s, faded away before multi-core/many-core became dominated. Therefore, we suggest memory chip vendors reconsider the VCM technology for multi-core/many-core architecture.
Year
DOI
Venue
2013
10.1109/TrustCom.2013.145
TrustCom/ISPA/IUCC
Keywords
Field
DocType
dram system performance,traditional dram chip,vcm technology,level parallelism,multimemory-controllers,leveraging memory,virtual channel memory,memory level parallelism,quality-of-service,memory chip vendor,quality of service,16-core system,parallel architectures,memory controller,modern multi-core,unexploited mlp,row buffer hit rate,dram chips,multiprocessing systems,qos,dram,dram system,multibank multirow-buffers,many-core architecture,mlp,rbhr,moore law,processor chip,memory controllers,multicore-many-core architecture,memory management,organizations,parallel processing,multicore processing
Dram,Registered memory,Interleaved memory,Computer science,Computer network,Universal memory,Computer hardware,Memory controller,Memory rank,Multi-channel memory architecture,CAS latency,Embedded system
Conference
ISSN
Citations 
PageRank 
2324-898X
1
0.35
References 
Authors
0
6
Name
Order
Citations
PageRank
Licheng Chen11039.74
Yongbing Huang2766.24
Yungang Bao336131.11
Guangming Tan443648.90
Zehan Cui519710.00
Ming-yu Chen690279.29