Name
Abstract | ||
|---|---|---|
The domain of vision and navigation often includes applications for feature tracking as well as simultaneous localization and mapping (SLAM). As these problems require computationally demanding solutions, it is challenging to achieve high performance without sacrificing the fidelity of results or otherwise consuming excessive amounts of energy. Our goal then is to accelerate the applications in this domain to meet real-time performance constraints while simultaneously reducing energy consumption and avoiding degradation in the quality of results. To achieve this domain-specific acceleration, we model a customizable hardware platform based on the 3D integration of a Field-Programmable Gate Array (FPGA) atop a standard chip multiprocessor (CMP) with Through-Silicon Vias (TSVs) used for communication between the two layers. Furthermore, partial automation of accelerator creation using C-to-RTL tools allows for analysis of a wide range of candidates. In this work, we mathematically characterize viable accelerator candidates, describe ideal application code for acceleration, and outline a dynamic-programming-based methodology for selecting an optimal set of candidates. Our results yield an overall speedup and energy reduction of 9.56X along with a 94X EDP reduction for the domain. Finally, we investigate the effects of various interconnect models on our performance improvements. Overall, our proposed system is shown to be highly efficient in both accelerating performance and saving energy for compute-intensive applications in this domain. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ASAP.2011.6043233 | ASAP |
Keywords | Field | DocType |
energy consumption,navigation application,edp reduction,domain-specific acceleration,overall speedup,performance improvement,customizable platform,accelerating performance,accelerator creation,accelerating vision,energy reduction,real-time performance constraint,high performance,acceleration,indexing terms,fpga,real time,real time systems,vision,navigation,dynamic programming,through silicon via,benchmark testing,feature extraction,field programmable gate array,field programmable gate arrays | Computer science,Parallel computing,Field-programmable gate array,Automation,Chip,Real-time computing,Gate array,Simultaneous localization and mapping,Energy consumption,Benchmark (computing),Embedded system,Speedup | Conference |
ISSN | Citations | PageRank |
2160-0511 | 6 | 0.53 |
References | Authors | |
23 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jason Cong | 1 | 7069 | 515.06 |
| B. Grigorian | 2 | 6 | 0.53 |
| G. Reinman | 3 | 21 | 1.75 |
| M. Vitanza | 4 | 6 | 0.53 |