Name
Abstract | ||
|---|---|---|
A novel implementation of a Two-dimensional FFT array processor is given. The reasons for its superior performance is the one-to-one and onto mapping of the problem communications topology onto the interconnection network, VLSI-based implementation, a proper choice for the number system, multiple-parallelism, and the use of packet-switching as opposed to circuit switching. A performance comparison also presented. |
Year | DOI | Venue |
|---|---|---|
1984 | 10.1145/800015.808162 | ISCA |
Keywords | Field | DocType |
two-dimensional fft array processor,interconnection network,proper choice,number system,circuit switching,novel implementation,problem communications topology,performance comparison,vlsi-based implementation,simd two-dimensional fft array,superior performance,circuit switched | Network processor,Circuit switching,Computer science,Parallel computing,SIMD,Real-time computing,Fast Fourier transform,Switched communication network,Interconnection,Vector processor,Very-large-scale integration | Conference |
Volume | Issue | ISSN |
12 | 3 | 0163-5964 |
ISBN | Citations | PageRank |
0-8186-0538-3 | 0 | 0.34 |
References | Authors | |
16 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mehrad Yasrebi | 1 | 7 | 2.03 |
| G. Jack Lipovski | 2 | 528 | 293.80 |