Name
Abstract | ||
|---|---|---|
In 1997, SEMATECH set off an alarm in the industry when it warned that productivity gains related to IC manufacturing capabilities (which increased at about 40% per year) outpaced the productivity gains in IC design capabilities (which increased at about 20% per year). In spite of this alarming gap between growing silicon capacity and design capabilities, the industry never felt the effects. Why? This invited talk reviews the findings from the 2012 Wilson Research Group Functional Verification Study and identifies the trends that prevented the design productivity gap. However, a more ominous challenge than the design productivity gap is emerging. While silicon capacity grows at a Moore's Law rate, verification effort grows at a double exponential rate, and the solutions used to close the design productivity gap will not be sufficient to close the verification productivity gap. This invited talk concludes with a discussion on the changes needed to overcome the verification productivity gap.
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Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ICCAD.2013.6691175 | ICCAD |
Keywords | Field | DocType |
design engineering,integrated circuit manufacture,2012 Wilson Research Group Functional Verification Study,IC design,IC manufacturing,Moore's Law,functional verification,productivity gains,productivity gap,functional verification | Ic manufacturing,Functional verification,Industrial engineering,Computer science,Electronic engineering,Integrated circuit design | Conference |
ISSN | ISBN | Citations |
1933-7760 | 978-1-4799-1069-4 | 2 |
PageRank | References | Authors |
0.37 | 0 | 1 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Harry Foster | 1 | 98 | 9.24 |