Name
Title | ||
|---|---|---|
Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/FPT.2009.5377641 | FPT |
Keywords | DocType | Citations |
parallel processing,reconfigurable architectures,system-on-chip,1Row design,ColHalf design,Dual Vt cells,LowHalf design,MuCCRA-3T,Mult design,MultSw design,Sw design,Sw+Half design,Sw+Mult design,coarse-grained dynamically reconfigurable processor arrays,leakage power reduction,performance degradation | Conference | 0 |
PageRank | References | Authors |
0.34 | 10 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Keiichiro Hirai | 1 | 0 | 0.34 |
| Masaru Kato | 2 | 13 | 2.68 |
| Yoshiki Saito | 3 | 35 | 4.52 |
| Hideharu Amano | 4 | 1375 | 210.21 |