Name
Abstract | ||
|---|---|---|
This paper describes optimization techniques using don't-care conditions that span the domain of high-level and logic synthesis. The following three issues are discussed: 1) how to describe and extract don't-care conditions from high-level descriptions; 2) how to pass don't-care conditions from high-level to logic synthesis; and 3) how to optimize the logic using don't-care conditions. Efficient techniques are given for these three problems which allow the use of large don't-care sets. Results from several examples demonstrate that these techniques are very effective for both area and delay minimization. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/ICCAD.1995.480023 | ICCAD |
Keywords | Field | DocType |
high level synthesis,logic design,don't-care conditions,high-level synthesis,logic synthesis,optimization techniques | Logic synthesis,Logic gate,Sequential logic,Logic optimization,Computer science,High-level synthesis,Programmable logic array,Theoretical computer science,Electronic engineering,Register-transfer level,Logic family | Conference |
ISSN | ISBN | Citations |
1092-3152 | 0-8186-7213-7 | 9 |
PageRank | References | Authors |
0.99 | 12 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| R. A. Bergamaschi | 1 | 174 | 16.90 |
| D. Brand | 2 | 292 | 84.65 |
| L. Stok | 3 | 27 | 3.68 |
| M. Berkelaar | 4 | 9 | 0.99 |
| S. Prakash | 5 | 24 | 3.23 |