Paper Info
Title
SPR: an architecture-adaptive CGRA mapping tool
Abstract
In this paper we present SPR, a new architecture-adaptive mapping tool for use with Coarse-Grained Reconfigurable Architectures (CGRAs). It combines a VLIW style scheduler and FPGA style placement and pipelined routing algorithms with novel mechanisms for integrating and adapting the algorithms to CGRAs. We introduce a latency padding technique that provides feedback from the placer to the scheduler to meet the constraints of a fixed frequency device with configurable interconnect. Using a new dynamic clustering method during placement, we achieved a 1.3x improvement in throughput of mapped designs. Finally, we introduce an enhancement to the PathFinder algorithm for targeting architectures with a mix of dynamically multiplexed and statically configurable interconnects. The enhanced algorithm is able to successfully share statically configured interconnect in a time-multiplexed way, achieving an average channel width reduction of .5x compared to non-shared static interconnect.
Year
DOI
Venue
2009
10.1145/1508128.1508158
FPGA
Keywords
Field
DocType
share statically,vliw style scheduler,enhanced algorithm,coarse-grained reconfigurable architectures,statically configurable interconnects,pipelined routing algorithm,pathfinder algorithm,fpga style placement,architecture-adaptive cgra mapping tool,new dynamic clustering method,new architecture-adaptive mapping tool,spr,scheduling,clustering,placement,routing
Scheduling (computing),Computer science,Very long instruction word,Parallel computing,Field-programmable gate array,Real-time computing,Throughput,Cluster analysis,Interconnection,Multiplexing,Padding,Embedded system
Conference
Citations 
PageRank 
References 
31
1.25
14
Authors
6
Name
Order
Citations
PageRank
Stephen Friedman1984.62
Allan Carroll2401.81
Brian Van Essen318315.53
Benjamin Ylvisaker4713.39
Carl Ebeling51405185.32
Scott Hauck62539232.71