Name
Abstract | ||
|---|---|---|
A low-power output feedback controlled frequency multiplier is proposed for Delay Locked Loop (DLL) based clock synthesizers. It uses N voltage controlled delay lines (VCDL) to multiply the input clock frequency by a factor of N/2. This frequency multiplier is less susceptible to jitter-accumulation. The proposed circuit can operate at a substantially low supply voltage. Simulation results show that the proposed frequency multiplier dissipates about 27% to 36% less power than other similar circuits. In addition, the proposed circuit can be easily programmed for generating various output clock frequencies. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ISCAS.2006.1692880 | 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS |
Keywords | Field | DocType |
jitter,low power electronics,delay locked loop,delay lock loop | Computer science,Control theory,Delay-locked loop,Clock domain crossing,Electronic engineering,Frequency multiplier,Clock skew,Synchronous circuit,Voltage multiplier,CPU multiplier,Clock rate | Conference |
ISSN | Citations | PageRank |
0271-4302 | 0 | 0.34 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Md. Ibrahim Faisal | 1 | 15 | 3.26 |
| Magdy A. Bayoumi | 2 | 803 | 122.04 |
| Peiyi Zhao | 3 | 96 | 9.81 |