Name
Title | ||
|---|---|---|
Low-overhead fault-tolerance technique for a dynamically reconfigurable softcore processor |
Abstract | ||
|---|---|---|
In this paper, we propose a new approach to implement a reliable softcore processor on SRAM-based FPGAs, which can mitigate radiation-induced temporary faults (single-event upsets (SEUs)) at moderate cost. A new Enhanced Lockstep scheme built using a pair of MicroBlaze cores is proposed and implemented on Xilinx Virtex-5 FPGA. Unlike the basic lockstep scheme, ours allows to detect and eliminate its internal temporary configuration upsets without interrupting normal functioning. Faults are detected and eliminated using a Configuration Engine built on the basis of the PicoBlaze core which, to avoid a single point of failure, is implemented as fault-tolerant using triple modular redundancy (TMR). A softcore processor can recover from configuration upsets through partial reconfiguration combined with roll-forward recovery. SEUs affecting logic which are significantly less likely than those affecting configuration are handled by checkpointing and rollback. Finally, to handle permanent faults, the tiling technique is also proposed. The new Enhanced Lockstep scheme requires significantly shorter error recovery time compared to conventional lockstep scheme and uses significantly smaller number of slices compared to known TMR-based design (although at the cost of longer error recovery time). The efficiency of the proposed approach was validated through fault injection experiments. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TC.2012.55 | IEEE Trans. Computers |
Keywords | Field | DocType |
roll-forward recovery,permanent fault handling,fault detection,softcore processor reliability,integrated circuit reliability,seu,checkpointing,tiling technique,xilinx virtex-5 fpga,configuration upset,microprocessor chips,microblaze cores,single-event upset (seu),internal temporary configuration upset detection,longer error recovery time,fault tolerant computing,single-event upset,internal temporary configuration upset,sram chips,reconfigurable architectures,low-overhead fault-tolerance technique,partial reconfiguration,softcore processor,shorter error recovery time,low-overhead fault tolerance technique,conventional lockstep scheme,rollback,dynamically reconfigurable softcore processor,system recovery,fault injection,fault diagnosis,tmr,logic design,error recovery,sram-based fpga,error recovery time,enhanced lockstep scheme,reconfigurable system,configuration upsets,redundancy,fpga,new enhanced lockstep scheme,basic lockstep scheme,field programmable gate arrays,lockstep,new approach,fault-tolerance,radiation-induced temporary fault mitigation,configuration engine,radiation effects,internal temporary configuration upset elimination,fault elimination,triple modular redundancy,picoblaze core,fault tolerance,hardware | MicroBlaze,Computer science,Parallel computing,Lockstep,Triple modular redundancy,Field-programmable gate array,PicoBlaze,Real-time computing,Fault tolerance,Control reconfiguration,Fault injection,Embedded system | Journal |
Volume | Issue | ISSN |
62 | 6 | 0018-9340 |
Citations | PageRank | References |
4 | 0.58 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hung-Manh Pham | 1 | 17 | 2.80 |
| Sebastien Pillement | 2 | 25 | 3.74 |
| Stanislaw J. Piestrak | 3 | 153 | 18.15 |