Name
Abstract | ||
|---|---|---|
The feasibility of a new transistor structure was demonstrated through an experimental observation of current gain and voltage gain. The proposed transistor structure is a hot electron transistor without a base layer to minimize scattering. Electron emission from the emitter is controlled using positively biased Schottky gate electrodes located on both sides of the emitter mesa. Monte Carlo simulation shows an estimated delay time of 0.17 ps and low gate leakage current with open-circuit voltage gain over unity. To confirm the basic operation, the device with a 25 nm wide emitter was fabricated. To obtain saturated current-voltage characteristics, the emitter was surrounded by gates and parasitic regions were eliminated by electron beam lithography. The observed open-circuit voltage gain was 25. To obtain a low leakage current, an electron energy smaller than the F-L separation was necessary to maintain the ballistic nature of the electron. When the gate-emitter voltage was 0.8 V, the gate leakage current was only 4% of the collector current. Thus voltage amplification and current amplification were confirmed simultaneously. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1093/ietele/e89-c.7.972 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
hot electron transistor, InP, ballistic electron, electron beam lithography | Leakage (electronics),Common emitter,Voltage,Optics,Electronic engineering,Electron-beam lithography,Transistor,Ballistic conduction,Physics,Open-circuit voltage,Electron | Journal |
Volume | Issue | ISSN |
E89C | 7 | 1745-1353 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yasuyuki Miyamoto | 1 | 1 | 4.68 |
| Ryo Nakagawa | 2 | 0 | 0.34 |
| Issei Kashima | 3 | 0 | 0.34 |
| Masashi Ishida | 4 | 0 | 0.34 |
| Nobuya Machida | 5 | 0 | 0.34 |
| Kazuhito Furuya | 6 | 1 | 1.30 |