Name
Abstract | ||
|---|---|---|
In this paper, we propose two 2's-complement fixed-width Booth multipliers that can generate an n-bit product from an n-bit multiplicand and an n-bit multiplier. Compared with previous designs, our multipliers have smaller truncation error, less area, and smaller time delay in the critical paths. A four-step approach is adopted to search for the best error-compensation bias in designing a multiplier suitable for VLSI implementation. Last but not least, we show the superior capability of our designs by inscribing it in a speech signal processor. Simulation results indicate that this novel design surpasses the previous fixed-width Booth multiplier in the precision of the product. An average error reduction of 65–84% compared with a direct-truncation fixed-width multiplier is achieved by adding only a few logic gates. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1093/ietfec/e90-a.6.1180 | IEICE Transactions |
Keywords | Field | DocType |
n-bit product,previous fixed-width booth multiplier,average error reduction,n-bit multiplier,fixed-width booth multiplier,smaller truncation error,smaller time delay,adaptive low-error fixed-width booth,direct-truncation fixed-width multiplier,digital signal processing,previous design,vlsi,n-bit multiplicand,logic gate,critical path,truncation error | Truncation error,Digital signal processing,Logic gate,Digital signal processor,Algorithm,Multiplier (economics),Multiplication,Very-large-scale integration,Mathematics,Booth's multiplication algorithm | Journal |
Volume | Issue | ISSN |
E90-A | 6 | 1745-1337 |
Citations | PageRank | References |
9 | 0.77 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Min-An Song | 1 | 15 | 2.44 |
| Lan-Da Van | 2 | 179 | 31.46 |
| Sy-Yen Kuo | 3 | 2304 | 245.46 |