Name
Title | ||
|---|---|---|
Application of BDDs in Boolean matching techniques for formal logic combinational verification |
Abstract | ||
|---|---|---|
Verifying that an implementation of a com- binational circuit meets its golden specification is an im- portant step in the design process. As inputs and out- puts can be swapped by synthesis tools or by interaction of the designer, the correspondence between the inputs and the outputs of the synthesized circuit and the in- puts and the outputs of the golden specification has to be restored before checking equivalence. In this paper, we re- view the main approaches to this isomorphism problem and show how to apply OBDDs in order to obtain efficient methods. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1007/s100090100039 | STTT |
Keywords | Field | DocType |
ce a,formal logic,design process | Boolean circuit,Computer science,Combinational verification,Theoretical computer science,Combinational logic,Isomorphism,Equivalence (measure theory),Engineering design process,And-inverter graph,Circuit minimization for Boolean functions | Journal |
Volume | Issue | Citations |
3 | 2 | 2 |
PageRank | References | Authors |
0.38 | 16 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Janett Mohnke | 1 | 91 | 7.03 |
| P. Molitor | 2 | 211 | 18.50 |
| Sharad Malik | 3 | 7766 | 691.24 |