Name
Abstract | ||
|---|---|---|
Solvers for propositional logic formulas, so called SAT solvers, are used in many practical applications. As multi-core and multi-processor hardware has become widely available, parallelizations of such solvers are actively researched. Such research typically ignores the incremental problem specification feature that modern SAT solvers possess. This feature is, however, crucial for many of the real-life applications of SAT solvers. Such applications include formal verification, equivalence checking, and typical artificial intelligence tasks such as scheduling, planning and reasoning. We have developed a multi-core SAT solver called Tarmo, which provides an interface that is compatible with conventional incremental solvers. It enables substantial performance improvements for many applications, without requiring code modifications. We present the asynchronous interface, a natural extension to the conventional solver interface that allows the construction of efficient application specific parallelizations. Through the asynchronous interface multiple problems can be given to the solver simultaneously. This enables conceptually simple but efficient parallelization of the solving process. Moreover, an asynchronous solver is easier to run in parallel with other independent tasks, simplifying the construction of so called coarse grained parallelizations. We provide an extensive experimental evaluation to illustrate the performance of the proposed techniques. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1007/978-3-642-36742-7_10 | TACAS |
Keywords | Field | DocType |
sat solvers,modern sat solvers,specific parallelizations,incremental sat,conventional incremental solvers,asynchronous interface,asynchronous interface multiple problem,coarse grained parallelizations,asynchronous solver,multi-core sat solver,conventional solver interface | Formal equivalence checking,Asynchronous communication,Scheduling (computing),Computer science,Boolean satisfiability problem,Propositional calculus,Theoretical computer science,Solver,Multi-core processor,Formal verification | Conference |
Volume | ISSN | Citations |
7795 | 0302-9743 | 5 |
PageRank | References | Authors |
0.44 | 24 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Siert Wieringa | 1 | 88 | 4.99 |
| Keijo Heljanko | 2 | 751 | 47.90 |