Paper Info
Title
High-Speed Reconfigurable Parallel System to Design Good Error Correcting Codes in Communications
Abstract
This paper presents a circuit that aids to accelerate the design of good error correcting codes in communications, where this design is a large optimization problem. The binary linear block codes detects and/or corrects the errors occurred during the data transmission. The problem to find a code that corrects a maximum number of errors is an optimization problem usually tackled by means of evolutionary algorithms and massive parallel computations. The circuit has been implemented on FPGA devices due to the easiness of the reconfigurable hardware to support real parallelism. The obtained results show that parallelizing the arithmetic operations involved in the fitness function improves the performance of a custom hardware solution in contrast to a software solution running on CPUs.
Year
DOI
Venue
2012
10.1007/s11265-011-0626-6
Signal Processing Systems
Keywords
Field
DocType
Error correcting codes,Hamming codes,FPGAs,Evolutionary algorithms,Parallelism
Hamming code,Concatenated error correction code,Evolutionary algorithm,Computer science,Low-density parity-check code,Parallel computing,Block code,Real-time computing,Linear code,Optimization problem,Reconfigurable computing
Journal
Volume
Issue
ISSN
66
2
1939-8018
Citations 
PageRank 
References 
2
0.36
6
Authors
3
Name
Order
Citations
PageRank
Juan A. Gómez-Pulido120221.36
Miguel A. Vega-Rodríguez2741113.05
Juan Manuel Sánchez-Pérez327830.84