Name
Abstract | ||
|---|---|---|
This paper presents the design and implementation of three dimensional (3D) Haar wavelet transform (HWT) with transpose based computation and dynamic partial reconfiguration (DPR) mechanism on field programmable gate array (FPGA). Due to the separability property of the multi-dimensional HWT, the proposed architecture has been implemented using a cascade of three N-point one dimensional (1D) HWT and two transpose memories for a 3D volume of NxNxN suitable for real-time 3D medical imaging applications. These applications require continuous hardware servicing, hence DPR has been introduced. Two architectures were synthesised using VHDL and implemented on Xilinx Virtex-5 FPGAs. Experimental results and comparisons between different configurations using partial and non-partial reconfiguration processes and a detailed performance analysis of the area, power consumption and maximum frequency are analysed in this paper. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1016/j.sysarc.2010.02.001 | Journal of Systems Architecture - Embedded Systems Design |
Keywords | Field | DocType |
haar wavelet transform (hwt),continuous hardware servicing,field programmable gate array,different configuration,efficient architecture,medical image processing,xilinx virtex-5 fpgas,multi-dimensional hwt,transpose memory,dynamic partial reconfiguration (dpr),non-partial reconfiguration process,dynamic partial reconfiguration,detailed performance analysis,real time,three dimensional | Transpose,Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Cascade,VHDL,Haar wavelet,Control reconfiguration,Computation,Power consumption | Journal |
Volume | Issue | ISSN |
56 | 8 | Journal of Systems Architecture |
Citations | PageRank | References |
5 | 0.47 | 12 |
Authors | ||
4 | ||