Paper Info
Title
A system for synthesizing optimized FPGA hardware from MATLAB
Abstract
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computations and meet time-to-market pressures. We present a compiler that takes as input algorithms described in MATLAB and generates RTL VHDL. The RTL VHDL then can be mapped to FPGAs using existing commercial tools. The input application is mapped to multiple FPGAs by parallelizing the application and embedding communication and synchronization primitives automatically. Our compiler infers the minimum number of bits required to represent the variable through a precision analysis framework. The compiler can leverage optimized IP cores to enhance the hardware generated. The compiler also exploits parallelism in the input algorithm by pipelining in the presence of resource constraints. We demonstrate the utility of the compiler by synthesizing hardware for a couple of signal/image processing algorithms and comparing them with manually designed hardware.
Year
DOI
Venue
2001
10.1109/ICCAD.2001.968639
ICCAD
Keywords
Field
DocType
input algorithm,optimized fpga hardware,ip core,fpga architecture,synthesizing hardware,rtl vhdl,multiple fpgas,behavioral description,efficient high level design,high throughput computation,input application,design of experiments,geometric programming,field programmable gate arrays,image processing,hardware description languages
High-level design,MATLAB,Computer science,Compiler correctness,Real-time computing,Computer hardware,Hardware description language,Pipeline (computing),Parallel computing,Field-programmable gate array,Compiler,VHDL,Embedded system
Conference
ISBN
Citations 
PageRank 
0-7803-7249-2
26
3.16
References 
Authors
16
4
Name
Order
Citations
PageRank
Malay Haldar19810.78
Anshuman Nayak29610.31
Alok Choudhary332231.06
Prith Banerjee425523.94