Paper Info
Title
REDEFIS: a system with a redefinable instruction set processor
Abstract
The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight performance or power constraints, or too complex to design in short TAT/TTM. REDEFIS is a HW/SW design platform for high level, efficient implementation of ASIPs/engines for SoC systems. It is composed of a reconfigurable instruction-set processor, capable to redefine its ISA according to the user application written in high level C language, and a set of design tools (an ISA Generator and a retargetable compiler). These processors can be used as flexible engines in embedded MPSoC systems, where its ISA is fully customized and design is done at high level C (no HDL writing is necessary). In this paper we present the Redefis design platform and an implementation of our dynamically reconfigurable ISA processor (codename Vulcan). Our results demonstrate the effectiveness of the system for encryption and bitwise applications.
Year
DOI
Venue
2006
10.1145/1150343.1150354
SBCCI
Keywords
Field
DocType
efficient implementation,soc system,c language,design tool,redefis design platform,dynamically reconfigurable isa processor,sw design platform,high level,soc design,redefinable instruction set processor,isa generator,soc
Computer architecture,Bitwise operation,Computer science,Instruction set,Production cost,Real-time computing,Compiler,Encryption,MPSoC,Embedded system
Conference
ISBN
Citations 
PageRank 
1-59593-479-0
0
0.34
References 
Authors
2
6
Name
Order
Citations
PageRank
Victor M. GOULART FERREIRA100.34
Lovic Gauthier215117.13
Takayuki KANDO351.35
Takuma MATSUO400.34
Toshihiko HASHINAGA500.34
Kazuaki Murakami639451.44