Name
Abstract | ||
|---|---|---|
In this paper, we designed a wide range DLL (Delay Locked Loop) for clock generator. A DLL-based clock generator has several inherent advantages over conventional PLL-based clock generators, such as no noise accumulation, fast lock and loop stability (1-st order loop filter). We propose a new DLL architecture to overcome a limited lock range. The proposed DLL is fabricated in a 0.25-mum n-well CMOS technology and an unlimited lock range is achieved. It operates in a reference signal of 5MHz to 100MHz, occupies 480x160mum(2) and dissipates only 5.8mW to generate 16-delayed clocks at 100MHz reference signal. It has only +/- 0.5% peak-to-peak jitters. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ISCAS.2004.1329119 | 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 4, PROCEEDINGS |
Keywords | Field | DocType |
phase detection,cmos technology,delay locked loop,jitter,detectors,phase locked loops,pulse generators,frequency,delay lock loop,pll,cmos integrated circuits | Phase-locked loop,Clock generator,Lock (computer science),Computer science,Delay-locked loop,CMOS,Electronic engineering,Pulse generator,Phase detector,Jitter | Conference |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kwangoh Kim | 1 | 2 | 1.07 |
| Nohman Park | 2 | 0 | 0.34 |
| Taekyu Kim | 3 | 14 | 4.89 |