Name
Title | ||
|---|---|---|
Topology-Aware Adaptive Routing for Nonstationary Irregular Mesh in Throttled 3D NoC Systems |
Abstract | ||
|---|---|---|
Three-dimensional network-on-chip (3D NoC) has been proposed to solve the complex on-chip communication issues in future 3D multicore systems. However, the thermal problems of 3D NoC are more serious than 2D NoC due to chip stacking. To keep the temperature below a certain thermal limit, the thermal emergent routers are usually throttled. Then, the topology of 3D NoC becomes a Nonstationary Irregular Mesh (NSI-Mesh). To ensure the successful packet delivery in the NSI-Mesh, some routing algorithms had been proposed in the previous works. However, the network still suffers from extremely traffic imbalance among lateral and vertical logic layer. In this paper, we propose a Topology Aware Adaptive Routing (TAAR) to balance the traffic load for NSI-Mesh in 3D NoC. TAAR has three routing modes, which can be dynamically adjusted based on the topology status of the routing path. In addition to increasing routing flexibility, the TAAR also increases both vertical and lateral path diversity to balance the traffic load. Compared with the related adaptive routing methods, the experimental results show that the proposed TAAR can reduce 19 to 295 percent traffic loads in the bottom logic layer and improve around 7.7 to 380 percent network throughput. According to our proposed VLSI architecture, the TAAR only needs less than 24.8 percent hardware overhead compared with the previous works. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TPDS.2012.291 | IEEE Trans. Parallel Distrib. Syst. |
Keywords | Field | DocType |
traffic load,traffic imbalance,transport layer assisted routing,complex on-chip communication,proposed taar,throttled 3d noc system,previous work,percent traffic,network routing,topology aware adaptive routing,microprocessor chips,network-on-chip,routing algorithm,vlsi architecture,nsi-mesh,topology-aware adaptive routing algorithm,three-dimensional integrated circuits,routing modes,three-dimensional network-on-chip,topology-aware adaptive routing,routing path,3d multicore system,3d noc,routing mode,vlsi,2d noc,proposed vlsi architecture,thermal problem,3d ic,noc systems,routing flexibility,logic layer,nonstationary irregular mesh,vertical logic layer,packet delivery,network on chip,routing,topology,network topology,nickel | Computer science,Static routing,Computer network,Real-time computing,Three-dimensional integrated circuit,Throughput,Very-large-scale integration,Distributed computing,Topology,Network packet,Network on a chip,Chip,Network topology | Journal |
Volume | Issue | ISSN |
24 | 10 | 1045-9219 |
Citations | PageRank | References |
3 | 0.39 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kun-Chih Chen | 1 | 45 | 6.28 |
| Shu-Yen Lin | 2 | 94 | 13.01 |
| Hui-Shun Hung | 3 | 10 | 1.15 |
| An-Yeu (Andy) Wu | 4 | 97 | 7.92 |