Name
Abstract | ||
|---|---|---|
For the FPGA Greedy Routing Architectures (GRAs), the optimal mapping problem of the entire chip can be decomposed into a sequence of three kinds of optimal m-side predetermined 4-way FPGA mapping problems, where m could be 1, 2, or 3. In this paper, we formulate the graph models of such sub-routing problems and investigate their minimum structures. The results give the lower bounds of routing resources in achieving all such kinds of GRAs and the theoretic models developed could be useful to studies on other FPGA routing problems as well. |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/ASPDAC.1998.669544 | PROCEEDINGS OF THE ASP-DAC '98 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 WITH EDA TECHNO FAIR '98 |
Keywords | Field | DocType |
chip,network routing,graph theory,switches,routing,field programmable gate arrays,computer architecture,computer science,lower bound | Graph theory,Graph,Link-state routing protocol,Dynamic Source Routing,Computer science,Static routing,Field-programmable gate array,Chip,Greedy algorithm,Electronic engineering | Conference |
Citations | PageRank | References |
0 | 0.34 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jiaofeng Pan | 1 | 12 | 1.71 |
| Yu-liang Wu | 2 | 316 | 37.60 |
| C. K. Wong | 3 | 0 | 0.34 |