Name
Title | ||
|---|---|---|
The design and synthesis of a synchronous and distributed MAC protocol for wireless network-on-chip |
Abstract | ||
|---|---|---|
To bridge the widening gap between computation requirements and communication efficiency faced by gigascale heterogeneous SoCs in the upcoming ubiquitous era, a new on-chip communication system, dubbed Wireless Network-on-Chip (WNoC), is introduced by using the recently developed CMOS proximity wireless interconnection technology. In this paper, a synchronous and distributed medium access control (SD-MAC) protocol is designed and implemented. Tailored for WNoC, SD-MAC employs a binary countdown approach to resolve channel contention between RF nodes. The receiver_select_sender mechanism and hidden terminal elimination scheme are proposed to increase the throughput and channel utilization of the system. Our simulation study shows the promising performance of SD-MAC in terms of throughput, latency, and network utilization. As a major component of simple and compact RF node design, a MAC unit implements the proposed SDMAC that guarantees correct operation of synchronized frames while keeping overhead low. The synthesis results demonstrate several attractive features such as high speed, low power consumption, nice scalability and low area cost.
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Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ICCAD.2007.4397332 | ICCAD |
Keywords | Field | DocType |
cmos integrated circuits,receiver_select_sender mechanism,low power consumption,new on-chip communication system,medium access control protocol,distributed mac protocol,gigascale heterogeneous soc,low area cost,network utilization,rf node,wireless network-on-chip,communication efficiency,cmos proximity wireless interconnection technology,mac protocol,on-chip communication system,compact rf node design,access protocols,channel contention,channel utilization,network-on-chip,overhead low,synchronous mac protocol,wireless network,network on chip,chip,high level synthesis,communication system | Wireless,Computer science,High-level synthesis,Computer network,Communications system,Network on a chip,Communication channel,Real-time computing,Throughput,Interconnection,Embedded system,Scalability | Conference |
ISSN | ISBN | Citations |
1092-3152 E-ISBN : 978-1-4244-1382-9 | 978-1-4244-1382-9 | 1 |
PageRank | References | Authors |
0.50 | 13 | 2 |